Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Insertion bonding is a technique whereby an electrical connection is formed between two components, e.g. between an integrated circuit and a carrier substrate. One of the components is provided with protruding contact structures, in the form of copper-based microbumps or so-called Through Silicon Vias (TSV). On the other component, a set of hollow contact areas is produced for receiving the bumps or TSVs. The contact areas are formed as cavities, lined with a metal layer and suitable for forming a connection with the metal of the bump or TSV, when the latter is brought into contact with the cavity under a given pressure.
The cavities are preferably provided with sloped sidewalls, so as to increase the accessibility of the cavity. A standard method for producing arrays of such cavities configured to receive an array of bumps or TSVs is to produce the cavities in a dielectric layer produced on top of a metallization layer, by a suitable etching technique, depositing a conformal metal layer (for example a stack of Ta and Cu), and removing the metal layer from the areas between the cavities by a litho/etch step, so as to isolate the cavities from each other. As a portion of the metal layer remains on the surface immediately surrounding the cavities, this technique makes it difficult to produce arrays with very small pitch (distance between corresponding points of two adjacent cavities, e.g. between two adjacent cavity center lines).
The currently known methods for producing the sloped sidewall surface of the cavities are also problematic. The standard etching technique used for creating these cavities utilizes an etching mask with openings that are smaller than the eventual top section of the cavities, taking into account a widening of the upper diameter of the openings due to underetching around the circumference of the mask openings when using a hardmask, or by the pull-back effect when using a resist as the mask (due to etching of the mask itself). This widening effect must be taken into account in the design of the etch mask, and represents another obstacle for producing fine-pitched arrays of cavities. Another method is shown in document US2005148180, where a resist layer is applied on top of a dielectric layer into which the cavities are to be produced, the resist layer being subsequently provided with openings, and heat treated to form sloped sidewalls in the openings. These sloped sidewalls are then transferred to the underlying layer by a suitable etching technique. This method however requires the additional heating step during which the slope of the openings is difficult to control. Especially when the height of the contact structures on the other component fluctuates significantly, this causes problems during the contacting process.